This invention is in the field of semiconductor non-volatile memories, and is more specifically directed to the manufacture of flash memories.
As well known in the art, “flash” memories are electrically-erasable semiconductor memory devices that can be erased and rewritten in relatively small blocks, rather than on a chip-wide or large-block basis as in previous electrically-erasable programmable read-only memory (EEPROM) devices. As such, flash memory has become especially popular for applications in which non-volatility (i.e., data retention after removal of power) of the stored data is essential, but in which the frequency of rewriting is relatively low. Examples of popular applications of flash memory include portable audio players, “SIM” card storage of telephone numbers and phone activity in cellular telephone handsets, USB flash drive removable storage devices for computers and workstations, storage cards for digital cameras, and the like.
An important recent advance in semiconductor non-volatile memory technology is the arrangement of the flash memory cells as “NAND” memory rather than “NOR” memory. As known in the art, NOR flash memory refers to the conventional arrangement of a column of memory cells in parallel between a bit line and a source line. Access of a specific cell in a NOR column is made by driving its word line (control gate) active while holding the other cells in the column off, so that the current between the bit line and source line is determined by the state of the accessed cell. Memory cells in a column of NAND memory, on the other hand, are connected in series between the bit line and the source line. Accessing of a specific cell in a NAND column thus requires turning on all of the cells in the column with active word line levels, and applying an intermediate word line level to the cell to be accessed, such that the current between the bit line and source line is, again, determined by the state of the accessed cell. As well known in the art, the chip area required per bit of NAND flash memory is much reduced from the area per bit of NOR flash memory, primarily because fewer conductors (and therefore contacts) are required for a column of NAND memory relative to NOR memory; in addition, access transistors can be shared among a large number of cells in the NAND arrangement. Additionally, conventional NAND flash memory is conveniently accessed serially, for example by sequentially accessing cells along the columns, rather than as a random access memory as in the case of NOR memory. NAND memory is thus especially well-suited for music and video storage applications
Another important recent advance in the field of flash memory is referred to in the art as the multilevel program cell (MLC). According to this approach, more than two data states are made possible for each memory cell, simply by more finely controlling the programming of the cell. In conventional binary data storage, each memory cell is programmed into either a “0” or a “1” state. Reading of such binary cells is accomplished by applying a single control voltage to the control gate of the addressed memory cell so that the transistor conducts if programmed to a “1” state, but remains off in the “0” state; sensing of the conduction through the addressed memory cell thus returns the programmed state of the cell. In contrast, according to a typical example of the MLC approach, four possible states are defined for each memory cell, typically corresponding to binary values 00, 01, 10, 11. In effect, the two intermediate states correspond to two levels of partial programming of the cell between the fully erased and fully programmed states. Some implementations of MLC flash memory with up to eight possible states, or three binary bits, per cell are known. The ability to store two or three bits of data on each memory cell immediately doubles or triples the data capacity of a flash memory chip. Examples of MLC flash memory cells and memories including such MLC cells are described in U.S. Pat. No. 5,172,338, and U.S. Pat. No. 6,747,892 B2, both commonly assigned herewith and incorporated herein by this reference.
The combination of MLC technology with the efficiencies of NAND flash memory architectures has resulted in significantly reduced cost per bit for semiconductor non-volatile storage. As a result, a wide range of new applications for flash memory have become feasible, up to and including mass data storage for personal computers, replacing magnetic disk drives.
MLC flash memories are thus achieved by changes in the programming and sensing operations, more so than by changes in the memory cell structure. As known in the art, the multi-level programming of conventional floating gate transistors is achieved primarily by varying the duration and number of programming pulses applied to the control gate of the floating-gate EEPROM transistor; the sequencing of programming voltages is another known approach to programming the various memory states. On the sensing side, the programmed data state of an MLC cell can be sensed by applying a single word line or control gate voltage to the cell, and comparing the resulting data state against multiple reference cells or reference levels to determine the data state of the cell. Such an approach is described in the above-referenced U.S. Pat. No. 5,172,338. Modern MLC memories sense the programmed data state of a cell by applying a sequence of control gate voltages to the accessed cell, with the sequence of results indicating the programmed state of the cell, as described in the above-referenced U.S. Pat. No. 6,747,892 B2.
A limiting factor in realizing MLC cells, and in increasing the data density of such cells, is the precision with which distinct data states may be programmed and sensed. To accomplish this, conventional MLC flash memories generate several analog voltages on-chip, including those analog voltages that are applied to the control gate to sense and program the desired memory cell state. In order to attain the necessary precision of these analog voltages, the manufacture and test of modern MLC flash memories can include “trimming”, or adjustment, of voltages internal to the flash memory device, for example during or after electrical test of the flash memory devices when still in wafer form. The flash memory devices themselves provide circuitry and interface capability (i.e., test pads at the die surface) to enable such trimming, as will now be described relative to FIG. 1.
FIG. 1 illustrates an architecture of a conventional flash memory device 2, in which the ability to trim analog voltages is provided. In device 2, flash memory array 4 includes a plurality of flash memory cells 3, each implemented by way of a floating-gate MOS transistor, arranged in rows and columns in the conventional manner. In this example, flash memory cells 3 correspond to the well-known NAND arrangement, although a NOR architecture may also be utilized. And, as is also conventional in the art especially for NAND flash memory, flash memory cells 3 are preferably of the multi-level cell (MLC) type, programmable into more than two states as discussed above. In this conventional memory device 2, control gate digital-to-analog converter (DAC) 6 receives multiple digital inputs, and generates control gate voltage Vcg accordingly; in the MLC arrangement, the digital inputs may be a representation of a control gate voltage Vcg to be applied to read or sense one of the MLC programmed states. Control gate voltage Vcg is generated by control gate DAC 6 accordingly, and is applied to row decoder 5 for application to the word line, or control gate, of a row of flash memory cells 3 to be read. Other fixed voltages (i.e., Vdd or ground) are applied to the gates, bit line, and source line, of the NAND arrangement of flash memory cells 3 in each selected column, as known in the art; one or more columns are then selected by column decoder 7 for sensing and output via sense amplifiers 13, in the conventional manner. Also in this conventional memory device 2, bandgap reference circuit 8 is also provided, for generating a reference voltage Vref from which such voltages as the programming pulses applied to the control gates of flash memory cells 3 are generated. Control logic 9 controls the operation of memory device 2, for example in response to one or more commands from a memory controller (not shown), in the example of NAND arrangement of flash memory cells 3.
Memory device 2 is trimmable, typically in wafer or die form, through the use of dedicated device “pads” of memory device 2. These pads are typically realized as aluminum or other metal pads at the chip surface of the integrated circuit embodying memory device 2, contactable by a conventional test probe. Alternatively, if desired, these pads may be bonded out to terminals or pins of the package of memory device 2, and thus accessible after packaging. In this conventional arrangement, particular analog voltages within memory device 2 can be directly monitored by way of such a pad. For example, control gate voltage Vcg as generated by control gate DAC 6 appears at probe pad Vcg TEST OUT PAD, and reference voltage Vref from bandgap reference circuit 8 appears at probe pad Vref TEST OUT PAD. As such, each of these analog voltages can be directly measured during operation by conventional test equipment. The trimming of these analog voltages may be effected by way of one or more instances of programmable impedance elements 11 in control gate DAC 6 and bandgap reference circuit 8. For example, programmable impedance elements 11 may be arranged in a voltage divider as shown, and programmable by the application of a programming voltage to corresponding device pads DAC PGM PAD for the programming of control gate DAC 6, and to pad BG PGM PAD for the programming of bandgap reference circuit 8. Examples of the construction and programming of programmable impedance elements 11 are described in U.S. Pat. No. 6,201,734 B1, issued Mar. 13, 2001, entitled “Programmable Impedance Device”, commonly assigned herewith and incorporated herein by this reference. Alternately, programmable impedance elements 11 may be implemented as fixed resistors in parallel or series with a transistor switch that can be turned on or off in response to a signal from a dedicated volatile latch (not shown). The latch may be loaded, for example, during the power initiation cycle or at other times, with a unique value stored in a dedicated ROM, EPROM, or EEPROM (not shown), or alternately from a memory location in the main flash memory array 3. The state of the latch is often referred to as a “fuse” even though the data may be physically stored as a cell value within a larger memory unit.
In operation of the conventional trimming of the analog voltages in memory device 2, therefore, test equipment measures the analog voltages Vcg and Vref at corresponding test pads Vcg TEST OUT PAD and Vref TEST OUT PAD. In the case of the control gate voltage Vcg, this measurement may be made at one or more of the possible analog output levels as determined by the application of the corresponding digital values at the input of control gate DAC 6. If the measured analog voltages are at levels other than nominal for the corresponding function, the conventional test equipment programs, or erases and reprograms, programmable impedance elements 11 in DAC 6 or bandgap reference circuit 8 (or sets values of “fuses”), and the corresponding analog voltage is measured again. Upon programming of the programmable impedance elements 11 to attain the desired analog voltages, memory device 2 is then ready for dicing, packaging, and completion of the manufacturing process in the conventional manner. The trimming of the analog voltages thus permits optimization of the performance and margins of memory device 2, compensating for variations in the manufacturing process.
In this conventional arrangement of FIG. 1, however, the probe pads for monitoring and trimming these of course occupy substantial chip area, not only for the pads themselves but also for the conductors that run to the pads. This additional chip area can be minimized by not providing conventional electrostatic discharge (ESD) protection devices for these pads (assuming that the pads are available only in die or wafer form, and not after packaging), but of course elimination of such protection devices renders memory device 2 vulnerable to ESD events at these test pads. In addition, in those instances in which the test pads are not available after packaging, any shift or change in device operation caused by the packaging of memory device 2 (e.g., package-induced stress effects on the silicon) cannot be compensated by further trimming, because the measuring and programming test pads are inaccessible after packaging.